Understanding the basics of setup and hold time

http://www.edn.com/design/analog/4371393/Understanding-the-basics-of-setup-and-hold-time

Understanding the basics of setup and hold time

http://www.edn.com/design/analog/4371393/Understanding-the-basics-of-setup-and-hold-time

How fixing max trans on clock path will impact timing {setup and hold}?

Ans: Fixing trans on clock path by up-sizing of buffers or inserting of buffers will decrease the insertion delay of a Flip-Flop.

Now consider the impact of insertion delay of FF on timing...........

Setup requirement equation:

tlaunch_insertion_delay + tcq + tcomb < tclk - tsetup + tcapture_insertion_delay

Hold requirement equation:

tlaunch_insertion_delay + tcq + tcomb > thold + tcapture_insertion_delay

Scenario-1: 

                 if u fix trans on diverge capture path it is going to worsen the setup requirement  and improves the hold requirement.

Scenario-2:

                if u fix trans on diverge launch path it is going to worsen the hold requirement and improves the setup requirement.

Scenario-3:

               if u fix trans on common path for launch & capture it is not going to show any impact on timing

Note: Fixing trans is going to show impact on skew

Tutorial for Bash shell

http://www.iitk.ac.in/LDP/LDP/abs/html/abs-guide.html

What "Levels of Logic" parameter refers in CTS report_QoR is?

This is the number of combinational logic cells present in the worst timing 
path. reports the number of logic levels by counting the number of times the attribute "@is_combinational" is set to "true" for the cells in the worst timing path.

What are power gating cells, and why are retention registers sometimes referred to as power gating cells?

Answer:

Power gating cells, also known as MTCMOS cells, power switch cells, power 
switches, or power management cells, are special library cells that act as a 
connection point between two voltage rails when they are turned on and a break 
point in the current path between the two rails when they are turned off. 
Turning off the power gating cells causes the switched rail (also known as the 
internal rail) to be disconnected from its source, or primary rail, which 
removes power from all cells connected to that switched rail. 

Power gating cells exist on the power or ground rails of one or more blocks in 
a design. They are either user-instantiated or inserted by either Jupiter-XT or 
IC Compiler. A power gating cell that switches the power net is sometimes 
referred to as a "header" cell, and a power gating cell that switches the 
ground net is sometimes referred to as a "footer" cell. 

Retention registers, by contrast, are a special form of sequential cell that 
can retain its state when the primary power net of the power domain's block 
(in which the cell exists) is powered down. Retention registers retain state 
by having two voltage rail pins: the primary voltage rail pin, which supplies 
power to the cell in its normal operating state, and the secondary (or backup) 
voltage rail pin, which supplies power to a low leakage state-saving latch 
within the sequential cell when the primary power is switched off.

Some versions of retention registers are known as State Retention Power Gating 
cells (or SRPG's), which is why retention registers are sometimes referred to as 
power gating cells. For clarity, it is recommended that you refer to state-saving
sequential cells as retention registers, and refer to the cells that connect and
disconnect a primary rail from a switched rail as power switches or power gates.

Handling complexities in clock gating checks

http://www.techonlineindia.com/article/12-07-16/handling_complexities_in_clock_gating_checks.aspx